The present invention relates to a technology capable of controlling the reflection of a transmission signal, which is caused by branch wirings (stub) in a memory module, and to a technology effective for application to a high-speed access-compatible memory module.
SSTL (Stub Series Terminated Transceiver Logic) has been known as a small-amplitude interface intended for a memory module. The SSTL has been described in, for example, English Paper Journal, VOL. E82-C, NO. 3, Yasuhiro KONISHI, et al., xe2x80x9cInterface technologies for Memories and ASICs-Review and Future Directionxe2x80x9d, issued by the Institute of Electronics, Information and Communication Engineers, March 1999.
A memory system using SSTL principally comprises a memory controller, signal wirings, connectors and memory modules mounted on a motherboard. The memory modules respectively have m memory chips provided on both surfaces of a module substrate. Data terminals of each individual memory chips are connected to their corresponding module data terminals in m units. Access control data terminals such as address terminals of the memory chips are connected to their corresponding module access control terminals. One-sided ends of the signal wirings are connected to their corresponding signal terminals of the memory controller, and the other ends thereof are terminated into a predetermined voltage. A plurality of memory modules are connected in parallel with their corresponding signal wirings through the connectors. Assuming now that the number of data terminals of each memory chip is defined as n and the number of the memory chips placed on the one side of each memory module is defined as m, the present memory system has mxc3x97n data signal wirings. The m memory chips placed on the one side of one memory module of plural memory modules are selected for one access according to a chip select signal generated by the memory controller. The ends or terminals of the signal wirings are connected to a terminal voltage through terminating resistors. Stub resistors for the memory controller are respectively series-connected to signal wirings for connecting the memory controller and the connectors.
Here, module wirings for connecting the module terminals of each memory module and the terminals of each memory chip constitute wirings which branch off from the signal wirings of the motherboard through the connectors. Stub resistors are placed in these module wirings. These stub resistors serve as matching loads for relaxing signal reflection developed in the signal wirings. Mismatching is generally developed in characteristic impedance at each wiring branch point. It is thus necessary to provide the stub resistors for relaxing the mismatching. Assuming that the characteristic impedance of each wiring is defined as Z0 and the characteristic impedance of each stub wiring is defined as Zs0, Zsxe2x80x94Z0/2 is suitable as the resistance value of each stub resistor. There is however the possibility that when the resistance value of the stub resistor increases, a voltage drop developed across the resistor will become great, thereby attenuating signal voltages such as addresses, data or the like and hence causing an error in a memory operation. When the resistance value of the stub resistor is less reduced to avoid the attenuation of the signal voltage for this season, there is the possible that signal reflection will become obvious in reverse and hence a signal waveform will disturb, thereby causing a malfunction in the same manner as described above. As the operation is made fast to increase a signal frequency and each branch wiring against which countermeasures are to be taken by the stub resistor, becomes long, the disturbance of a signal waveform at a receiving end becomes great.
On the other hand, the present inventors have discussed, as another memory system, a type wherein a plurality of memory modules are series-connected via connectors to their corresponding signal wirings connected to a memory controller on a motherboard. The present inventors have discussed a configuration wherein on a memory module, a plurality of memory chips are connected by one-stroke writable wiring paths through data signal wirings. Assuming that the number of data signal terminals of each memory element is defined as n in the present memory system, n module data signal wirings are provided therein regardless of the number m of memory elements placed on one side of each memory module, and one memory chip of the plural memory chips is selected for one access.
In another memory system referred above, all the memory modules are series-connected to their corresponding signal wirings of the motherboard, and the module signal wirings lying within the memory modules are series-connected to all the memory chips arranged in a line and are laid along the longitudinal direction of each memory module. Thus, a problem decreases that as in the case of the SSTL, the memory modules little form the branch wirings with respect to the signal wirings on the motherboard, and the disturbance of each waveform due to undesired signal reflection caused by the branch wirings occurs.
However, the present inventors have revealed that the length of the signal wiring increases, and the time necessary for the signal to propagate from the memory controller to the corresponding memory chip at the farthest end thereof becomes long, thus increasing a delay in access time.
Thus, a problem arises in that the module wirings of each memory module constitute the branch wirings on the memory system in the case of the SSTL type, whereby the malfunction due to the signal reflection caused thereby occurs and the speeding up of the memory operation is limited. Since such branching for the signal wiring as developed in the SSTL little exists in the memory module of such a type that the memory chips are connected in series, the branch wiring-based problem decreases. However, the present inventors have revealed the possibility that an increase in the length of the signal wiring lying within each memory module will cause a delay in access time and cannot cope with higher-speed access.
After the completion of the invention of the present application, the inventors of the present application have recognized the following examples known to date. Japanese Patent Application Laid-Open Nos. Hei 5(1993)-234355 and 6(1994)-150085 respectively have disclosed the invention wherein connectors are provided at both long-side portions of each memory module so that the plural memory modules can be connected in tandem. However, they do not disclose a wiring structure provided inside each memory module. Japanese Patent Application Laid-Open No. Hei 7(1995)-334415 discloses a memory module having extended connectors which allow cascade connections of extended memory modules. Japanese Patent Application Laid-Open No. Hei 7(1995)-261892 discloses the invention wherein each of memory modules is provided with inlet connectors and outlet connectors, a memory bus on the memory module connects between them, and memory elements are connected in series with the memory bus, whereby undesired signal reflection is controlled. However, the first through third known examples merely provide the technology of the cascade-connectable memory modules. The fourth known example merely shows the system for connecting the plural memory elements to their corresponding memory bus on each memory module in series form. Any of the examples does not provide the conception leading to the invention of the present application.
The present invention aims to provide a memory module capable of controlling the disturbance of a signal waveform due to signal reflection to improve the reliability of signal transmission and restraining an increase in access time.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be explained in brief as follows:
[1] A memory module comprises a module substrate, and a plurality of memory chips mounted on the module substrate and respectively having a plurality of chip data terminals. The module substrate has a plurality of module data terminal pairs individually provided in association with the respective chip data terminals included in the plurality of memory chips, and a plurality of module data wirings which respectively connect between the plurality of module data terminal pairs. The plurality of module data wirings are connected to their corresponding chip data terminals and are configured so as to be available as a memory access data bus.
Since the module data wirings on the memory module constitute the memory access data bus in the memory module, the module data wirings of the respective memory modules are connected in sequential form in a memory system in which a plurality of memory modules are connected in series. Further, each individual module data wirings do not constitute branch wirings with respect to the data bus on the motherboard of the memory system. Thus, such signal reflection as caused by branching to the data bus on the motherboard of the memory system is not developed. Further, since the chip data terminals are directly connected to the module data wirings on each memory module, such signal reflection as caused by branching to the module data wirings is also developed. In the memory module, parallel access for the number of bits corresponding to the width of the memory access data bus is assured. Thus, the disturbance of each signal waveform due to the signal reflection is restrained while an increase in access time is being controlled, thereby to allow an increase in reliability of signal transmission.
The standpoint that the plurality of module data wirings are regarded as the single memory access data bus, can be grasped from the viewpoint that the plurality of memory chips are chip-selected and controlled on a parallel basis.
Various forms may be adopted as specific forms of module data terminal pairs and module data wirings. Firstly, when the plurality of memory chips may be arranged along the longitudinal direction of the module substrate, the module data terminal pairs are placed at one long-side portions and the other long-side portions of each individual memory chip-mounted surfaces of the module substrate. In other words, the module data wirings may be caused to extend from one long-side portion of each memory chip-mounted surface of the module substrate to the other long-side portion thereof. In a further viewpoint, the plurality of module data wirings may be grasped as those respectively have lengths each substantially equal to the length of the short side of the module substrate. Thus, the length of each module data wiring becomes consequentially short and the parasitic capacitance of each wiring and the resistance thereof are reduced.
Secondly, when the plurality of memory chips are arranged along the longitudinal direction of the module substrate, the module data terminal pairs may be placed at one long-side portion of the module substrate. Described specifically, the module data wirings are formed in the same wiring layer on a return or reciprocating basis and connected to their corresponding module data terminal pairs. Further, the module data wirings are formed in mutually-different wiring layers brought into conduciton through holes defined between the wiring layers and are connected to their corresponding module data terminal pairs.
Thirdly, the memory chips may be placed on both surfaces of the module substrate so as to constitute each memory module.
[2] A memory module comprises a module substrate, and a plurality of memory chips mounted along the longitudinal direction of the module substrate and respectively having a plurality of chip data terminals and a plurality of chip address terminals. The module substrate has a plurality of module data terminal pairs individually provided in association with the respective chip data terminals included in the plurality of memory chips, module address terminal pairs common to the plurality of memory chips, a plurality of module data wirings which respectively connect the plurality of module data terminal pairs in linear form, and module address wirings which connect the module address terminal pairs in linear form and which extend in intersecting directions and are commonly connected to the chip address terminals of the plurality of memory chips. The plurality of module data wirings are connected to their corresponding chip data terminals.
According to the above means, the disturbance of each signal waveform due to signal reflection is restrained while an increase in access time is being controlled, thereby to allow an increase in reliability of signal transmission in the same manner as described above. In particular, this contributes to the shortening of the lengths of the module data wiring and the module address wiring.
The module address wirings extend in directions orthogonal to the linear wiring portions for connecting the module address terminal pairs and distribute address signals to their corresponding chip address terminals of the plural memory chips. Therefore, if address buffer circuits are interposed in the module address wirings and configured in parts as first module address wirings which connect the module address terminal pairs in linear form and are connected with input terminals of the address buffer circuits, and second module address wirings which are commonly connected to the plural chip address terminals from output terminals of the address buffer circuits and are respectively placed in directions orthogonal to the first module address wirings, it is then possible to restrain the formation of innegligible impedance mismatching on each module address wiring. In short, branching to the second module address wirings disappears from above the first module address wirings.
The second module address wirings may be connected to their corresponding terminating voltage terminals through resistive elements having their characteristic impedances. Thus, the ends of the second module wirings are matched and terminated. It is therefore possible to restrain the disturbance of each waveform due to signal reflection in the corresponding wiring.
The data terminals may be placed so as to be shifted between at least adjacent terminals as viewed in the direction in which the module data wirings extend. Similarly, the address terminals may be placed so as to be shifted between at least adjacent terminals as viewed in the direction in which the module address wirings extend. It becomes easy to form contacts between the chip data terminals and module data wirings and contacts between the chip address terminals and module address wirings.
[3] If the module data wirings are positively expressed as free of their branching per se, then the module data wirings may be grasped as those having one-stroke writable wiring paths or routes.
If actual signal reflection is taken into consideration, then no undesired signal reflection is developed if the following conditions are met, then no undesired signal reflection is developed for the most part. Namely, the module data wirings have one-stroke writable first wiring paths and second wiring paths which branch off from the first wiring paths and are connected to the module data terminals. The length of each second wiring path is set in such a manner that the time necessary for a signal for ensuring a normal operation to move forward and backward alternately along the second wiring path becomes shorter than a state transition time of the signal.
[4] In a memory module, the following means may be adopted as means for relatively easily implementing the connections between chip connecting terminals and module wirings vertically and horizontally placed in each memory chip in large numbers. Namely, the memory module has a module substrate, and a plurality of memory chips placed along the longitudinal direction of the module substrate and respectively having a plurality of chip connecting terminals. The module substrate has a plurality of module connecting terminals provided in association with the chip connecting terminals included in the plurality memory chips, and module wirings which respectively connect the module connecting terminals and the chip connecting terminals. The module wirings bypass predetermined chip connecting terminals of the plural chip connecting terminals placed in linear form, so as to connect to other predetermined chip connecting terminals.